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Integrator Logic Tiles

In conjunction with the RealView Versatile and Integrator families, Logic Tiles enable system-on-chip (SoC) developers to prototype complete systems, prove custom IP and develop and test device drivers for custom IP. Logic Tiles may be stacked to provide additional capacity. High performance and high pin-count interconnect allows large design prototyping.

Software developed for the Logic Tile based prototype hardware can be executed and debugged using ARM's debug and trace tools, in conjunction with RealView ICE or RealView Trace. ARM Standard debug and trace connections are provided by the Versatile Platform Baseboard or Integrator Interface Module for Integrator Logic Tiles (IM-LT1).

Architecture

• Xilinx Virtex-II FPGA, XC2V6000 or XC2V8000
• New Integrator Logic Tile form factor
• 2 Programmable clock generators on-tile
• Compatible with the Versatile Platform Baseboard for ARM926EJ-S
• Compatible with Integrator ASIC Platform (Integrator/AP)and Integrator Compact platform (Integrator/CP) using Integrator IM-LT1

Memory System

• Two 32-bit wide 2MB ZBT SSRAM devices per Logic Tile
• 8MB flash memory used for FPGA Configuration Data (Multi-ICE unit required to program flash memory)

Debug Capability

• RealView ICE and RealView Trace ready
• Requires Multi-ICE to program configuration flash

I/O

• Logic Tile Header connectors on top & bottom of each tile
• 395 interconnect pins to tile above
• 395 interconnect pins to tile below
• 128 interconnect pins common to tiles above and below
• Option to fold over some signals to increase I/O to tile below
• 4 DIP switches and 4 general purpose LEDs
• Pushbutton

Power Supply

• Integrator Logic Tiles require 3.3V and 5V

Scalability

• Integrator Logic Tiles may be stacked
• Logic Tiles can be connected to Integrator family boards using the Integrator/IM-LT1 Interface Module
• Logic Tiles interface directly to the Versatile Platform Baseboard for ARM926EJ-S, without an adapter

FPGA Design Software

• Xilinx Virtex II compatible FPGA tools may be used with Logic Tiles